The time delay before this change occurs is equal to the sum of the gate delays g 4 and g 1 and is the set-up time for the flip-flop. When the data D is changed from 0 → 1 during the asynchronous period then the output of g 4 changes from 1 → 0 which initiates a 0 → 1 transition at the output of g 1 and that change is transferred to the input of g 2 as shown in Figure 6.21(b). If additionally D = 0, then the remaining signals at different parts of the circuit can easily be determined, and they have been inserted in Figure 6.21(b). In order to maintain the output latch in a stable state, both S ¯ and R ¯ must be held at 1 and this is achieved when the clock Ck = 0 since the outputs of g 2 and g 3 are then 1. The output latch is formed by gates g 5 and g 6. The three latches are interconnected as shown in Figure 6.21(b), with g 1 and g 2 comprising one latch while g 3 and g 4 comprise a second latch. The diagram shows the effect of a 0 → 1 transition on the D line (c) Effect of a 0 → 1 transition on the clock line (a) The basic S ¯ R ¯ flip-flop (b) Edge triggered flip-flop.
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